A programmable logic device (PLD) is a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. Examples of PLDs include the field programmable gate array (FPGA), and the complex programmable logic device (CPLD). PLDs typically include various programmable resources such as configurable logic blocks (CLBs), function blocks, programmable input/output blocks (IOBs), and a programmable interconnect structure. Some PLDs also include additional programmable resources (e.g., DLLs, RAM, multipliers, processors, transceivers).
The programmable resources of a PLD are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells. The collective states of the individual memory cells then determine the function of the PLD. The data bits can be stored in volatile memory, such as static RAM (SRAM) cells, in non-volatile memory, such as flash memory or electrically erasable programmable read-only memory (EEPROM), or in any other type of memory cell. The memory cells can be part of an external device, such as an external PROM, or can be located on-chip. It can be advantageous to store such configuration information in nonvolatile memory because the configuration information persists even after electrical power is disconnected from a particular device.
In some situations, however, EEPROM cells can be slower and can consume more power than SRAM cells. For example, some EEPROM cells require a sense amplifier, which can consume a significant amount of power, to detect or retrieve stored data. SRAM, on the other hand, can typically provide the stored data without such sense amplifiers. Furthermore, SRAM cells, although volatile, can be faster than EEPROM cells. Thus, in contrast to EEPROMs, SRAM cells can consume relatively little power with improved performance while enabled and operating.
To address this power and performance problem, and other problems, some PLDs, including some CPLDs, use both volatile and nonvolatile memory. Such PLDs include the CoolRunner II family of CPLDs available from Xilinx, Inc. of San Jose, Calif. In these PLDs, configuration data is stored on-chip (or sometimes on an external chip) in non-volatile memory, and is downloaded to volatile memory as part of an initialization sequence. The process by which configuration information persistently stored in nonvolatile memory (e.g., EEPROM) is transferred to volatile memory (e.g., SRAM) upon initialization of the PLD is known as configuration loading (“conloading”). Using both types of memory to configure a PLD exploits the performance advantages of SRAM when the PLD is in operation, while still allowing the PLD to be powered down with no loss of configuration data by storing the data in nonvolatile memory.
PLDs having both volatile and nonvolatile memory, however, suffer from several drawbacks. First, the conloading process depends on reliably detecting power-up, which can be difficult. If, for example, the power supply powering the PLD does not power up smoothly, conloading may start before there is sufficient power to properly read from the nonvolatile memory, or write to the volatile memory. Also, in some CPLD target systems, particularly target systems having multiple system voltages, it can take a significant period of time for the target system to reach an initial stable system power level. Furthermore, once the power supply is stabilized, such PLDs are not ready for operation until all of the configuration information has been transferred from the nonvolatile memory to the volatile memory (i.e., the conloading process is complete), further delaying startup. This transfer or initialization process can take from approximately 20 μs to approximately 100 μs, and, in some cases can take much longer, for example up to 1 second.
Another disadvantage in using both volatile and nonvolatile memory is the increased burden on limited system resources. Having two sets of memories means that either additional area is consumed on the PLD, if on-chip memory is used, or an additional external device must be placed in the system for off-chip memory. Also, additional control circuitry and overhead must be designed and implemented to manage the conloading process and ensure synchronization between the two sets of memories. All of these factors can contribute to increased design and manufacturing costs.
To address the disadvantages of the conloading process, a special EEPROM cell that combines the performance benefits of tradition SRAM cells with the persistence of a traditional EEPROM cell can be used to configure the PLD directly. This eliminates the conloading step, and the delay, overhead, and other disadvantages associated with that process. One example of such an EEPROM cell, and a description of its operation, is set forth in U.S. Pat. No. 5,272,368 to Turner et al., which is incorporated herein by reference.
An example of a prior art EEPROM cell 100 (consistent with the cell disclosed by Turner et al.) is shown in FIG. 1A. EEPROM cell 100 comprises an access gate 105, a tunnel capacitor 107 (shown as a transistor since it is formed like a transistor), a control gate 121, a floating gate 133, and inverters 140 (comprising transistors 141 and 144) and 150. Tunnel capacitor 107 typically has a very thin oxide layer, in some cases approximately 85 Angstroms. Floating gate 133 is a polysilicon (poly) layer shared between tunnel capacitor 107 and inverter 140. Data is stored in EEPROM cell 100 by injecting and storing a charge on floating gate 133, and can be read or detected through inverters 140 and 150. Control gate 121 controls the process for injecting or removing a charge on floating gate 133. One advantage of this arrangement is that data can be read without additional sense amplifiers, thereby conserving power. Inverters 140 and 150 provide a rail-to-rail output, and eliminate the need for sense amplifiers. Details regarding programming, erasing, and reading EEPROM cell 100 can be found in the above-referenced patent to Turner et al.
FIG. 1B shows a top view of a layout 180 of EEPROM cell 100 (note that inverter 150 is not shown for clarity). In layout 180, tunnel capacitor 107 and control gate 121 are formed in a single polysilicon layer. Floating gate 133, at the input of inverter 140, is also formed in the same polysilicon layer. Since tunnel capacitor 107 requires a very thin oxide, control gate 121 and floating gate 133 (formed in the same poly layer) have the same thin oxide.
Area on an integrated circuit is always at a premium, and minimizing the area of an IC without sacrificing performance or functionality is always a goal in designing ICs. As IC area is reduced, the cost of manufacturing an IC is also reduced. A disadvantage of the prior art single poly EEPROM cell described above is that it does not easily lend itself to an efficient layout, and can therefore be difficult to shrink as process technology improves. One reason for this disadvantage is the coupling capacitance requirement for such EEPROM cells. The coupling ratio relates the coupling capacitance of the control gate to the capacitance of the tunnel capacitor. Generally, a high coupling ratio is necessary to ensure that most of the high voltage difference applied to the EEPROM cell can be applied to the floating gate. High voltage differences are needed at the floating gate in order to program and erase the EEPROM cell.
Furthermore, the prior art single poly EEPROM cell is susceptible to reliability problems due to the thin oxide layer required by the tunnel capacitor. For instance, the prior art cell can have data retention issues, wherein the oxide degrades over time due to the high voltages used. The thin oxide of the prior art EEPROM cell can also lead to read and/or write errors in the memory cell.
Therefore, a need exists for a low-power EEPROM cell having a high coupling ratio that is area efficient, reliable and easily shrinkable.